mirror of
https://github.com/Jous99/F4MP.git
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468 lines
17 KiB
C
468 lines
17 KiB
C
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// file: source/threading/atomic.c
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#ifdef ZPL_EDITOR
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#include <zpl.h>
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#endif
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ZPL_BEGIN_C_DECLS
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////////////////////////////////////////////////////////////////
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//
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// Concurrency
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//
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//
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// IMPORTANT TODO: Use compiler intrinsics for the atomics
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#if defined(ZPL_COMPILER_MSVC) && !defined(ZPL_COMPILER_CLANG)
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zpl_i32 zpl_atomic32_load (zpl_atomic32 const *a) { return a->value; }
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void zpl_atomic32_store(zpl_atomic32 *a, zpl_atomicarg(zpl_i32) value) { a->value = value; }
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zpl_i32 zpl_atomic32_compare_exchange(zpl_atomic32 *a, zpl_atomicarg(zpl_i32) expected, zpl_atomicarg(zpl_i32) desired) {
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return _InterlockedCompareExchange(cast(long *)a, desired, expected);
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}
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zpl_i32 zpl_atomic32_exchange(zpl_atomic32 *a, zpl_atomicarg(zpl_i32) desired) {
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return _InterlockedExchange(cast(long *)a, desired);
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}
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zpl_i32 zpl_atomic32_fetch_add(zpl_atomic32 *a, zpl_atomicarg(zpl_i32) operand) {
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return _InterlockedExchangeAdd(cast(long *)a, operand);
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}
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zpl_i32 zpl_atomic32_fetch_and(zpl_atomic32 *a, zpl_atomicarg(zpl_i32) operand) {
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return _InterlockedAnd(cast(long *)a, operand);
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}
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zpl_i32 zpl_atomic32_fetch_or(zpl_atomic32 *a, zpl_atomicarg(zpl_i32) operand) {
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return _InterlockedOr(cast(long *)a, operand);
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}
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zpl_i64 zpl_atomic64_load(zpl_atomic64 const *a) {
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#if defined(ZPL_ARCH_64_BIT)
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return a->value;
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#elif ZPL_CPU_X86
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// NOTE: The most compatible way to get an atomic 64-bit load on x86 is with cmpxchg8b
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zpl_atomicarg(zpl_i64) result;
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__asm {
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mov esi, a;
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mov ebx, eax;
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mov ecx, edx;
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lock cmpxchg8b [esi];
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mov dword ptr result, eax;
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mov dword ptr result[4], edx;
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}
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return result;
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#else
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#error TODO: atomics for this CPU
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#endif
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}
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void zpl_atomic64_store(zpl_atomic64 *a, zpl_atomicarg(zpl_i64) value) {
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#if defined(ZPL_ARCH_64_BIT)
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a->value = value;
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#elif ZPL_CPU_X86
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// NOTE: The most compatible way to get an atomic 64-bit store on x86 is with cmpxchg8b
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__asm {
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mov esi, a;
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mov ebx, dword ptr value;
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mov ecx, dword ptr value[4];
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retry:
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cmpxchg8b [esi];
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jne retry;
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}
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#else
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#error TODO: atomics for this CPU
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#endif
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}
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zpl_i64 zpl_atomic64_compare_exchange(zpl_atomic64 *a, zpl_atomicarg(zpl_i64) expected, zpl_atomicarg(zpl_i64) desired) {
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return _InterlockedCompareExchange64(cast(zpl_atomicarg(zpl_i64) *)a, desired, expected);
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}
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zpl_i64 zpl_atomic64_exchange(zpl_atomic64 *a, zpl_atomicarg(zpl_i64) desired) {
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#if defined(ZPL_ARCH_64_BIT)
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return _InterlockedExchange64(cast(zpl_atomicarg(zpl_i64) *)a, desired);
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#elif ZPL_CPU_X86
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zpl_atomicarg(zpl_i64) expected = a->value;
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for (;;) {
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zpl_atomicarg(zpl_i64) original = _InterlockedCompareExchange64(cast(zpl_atomicarg(zpl_i64) *)a, desired, expected);
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if (original == expected)
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return original;
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expected = original;
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}
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#else
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#error TODO: atomics for this CPU
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#endif
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}
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zpl_i64 zpl_atomic64_fetch_add(zpl_atomic64 *a, zpl_atomicarg(zpl_i64) operand) {
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#if defined(ZPL_ARCH_64_BIT)
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return _InterlockedExchangeAdd64(cast(zpl_atomicarg(zpl_i64) *)a, operand);
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#elif ZPL_CPU_X86
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zpl_atomicarg(zpl_i64) expected = a->value;
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for (;;) {
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zpl_atomicarg(zpl_i64) original = _InterlockedCompareExchange64(cast(zpl_atomicarg(zpl_i64) *)a, expected + operand, expected);
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if (original == expected)
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return original;
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expected = original;
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}
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#else
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#error TODO: atomics for this CPU
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#endif
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}
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zpl_i64 zpl_atomic64_fetch_and(zpl_atomic64 *a, zpl_atomicarg(zpl_i64) operand) {
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#if defined(ZPL_ARCH_64_BIT)
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return _InterlockedAnd64(cast(zpl_atomicarg(zpl_i64) *)a, operand);
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#elif ZPL_CPU_X86
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zpl_atomicarg(zpl_i64) expected = a->value;
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for (;;) {
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zpl_atomicarg(zpl_i64) original = _InterlockedCompareExchange64(cast(zpl_atomicarg(zpl_i64) *)a, expected & operand, expected);
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if (original == expected)
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return original;
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expected = original;
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}
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#else
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#error TODO: atomics for this CPU
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#endif
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}
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zpl_i64 zpl_atomic64_fetch_or(zpl_atomic64 *a, zpl_atomicarg(zpl_i64) operand) {
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#if defined(ZPL_ARCH_64_BIT)
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return _InterlockedOr64(cast(zpl_atomicarg(zpl_i64) *)a, operand);
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#elif ZPL_CPU_X86
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zpl_atomicarg(zpl_i64) expected = a->value;
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for (;;) {
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zpl_atomicarg(zpl_i64) original = _InterlockedCompareExchange64(cast(zpl_atomicarg(zpl_i64) *)a, expected | operand, expected);
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if (original == expected)
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return original;
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expected = original;
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}
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#else
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#error TODO: atomics for this CPU
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#endif
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}
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#elif defined(ZPL_CPU_X86)
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zpl_i32 zpl_atomic32_load (zpl_atomic32 const *a) { return a->value; }
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void zpl_atomic32_store(zpl_atomic32 *a, zpl_atomicarg(zpl_i32) value) { a->value = value; }
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zpl_i32 zpl_atomic32_compare_exchange(zpl_atomic32 *a, zpl_atomicarg(zpl_i32) expected, zpl_atomicarg(zpl_i32) desired) {
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zpl_atomicarg(zpl_i32) original;
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__asm__(
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"lock; cmpxchgl %2, %1"
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: "=a"(original), "+m"(a->value)
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: "q"(desired), "0"(expected)
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);
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return original;
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}
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zpl_i32 zpl_atomic32_exchange(zpl_atomic32 *a, zpl_atomicarg(zpl_i32) desired) {
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// NOTE: No lock prefix is necessary for xchgl
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zpl_atomicarg(zpl_i32) original;
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__asm__(
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"xchgl %0, %1"
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: "=r"(original), "+m"(a->value)
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: "0"(desired)
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);
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return original;
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}
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zpl_i32 zpl_atomic32_fetch_add(zpl_atomic32 *a, zpl_atomicarg(zpl_i32) operand) {
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zpl_atomicarg(zpl_i32) original;
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__asm__(
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"lock; xaddl %0, %1"
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: "=r"(original), "+m"(a->value)
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: "0"(operand)
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);
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return original;
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}
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zpl_i32 zpl_atomic32_fetch_and(zpl_atomic32 *a, zpl_atomicarg(zpl_i32) operand) {
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zpl_atomicarg(zpl_i32) original;
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zpl_atomicarg(zpl_i32) tmp;
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__asm__(
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"1: movl %1, %0\n"
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" movl %0, %2\n"
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" andl %3, %2\n"
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" lock; cmpxchgl %2, %1\n"
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" jne 1b"
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: "=&a"(original), "+m"(a->value), "=&r"(tmp)
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: "r"(operand)
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);
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return original;
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}
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zpl_i32 zpl_atomic32_fetch_or(zpl_atomic32 *a, zpl_atomicarg(zpl_i32) operand) {
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zpl_atomicarg(zpl_i32) original;
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zpl_atomicarg(zpl_i32) temp;
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__asm__(
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"1: movl %1, %0\n"
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" movl %0, %2\n"
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" orl %3, %2\n"
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" lock; cmpxchgl %2, %1\n"
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" jne 1b"
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: "=&a"(original), "+m"(a->value), "=&r"(temp)
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: "r"(operand)
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);
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return original;
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}
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zpl_i64 zpl_atomic64_load(zpl_atomic64 const *a) {
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#if defined(ZPL_ARCH_64_BIT)
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return a->value;
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#else
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zpl_atomicarg(zpl_i64) original;
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__asm__(
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"movl %%ebx, %%eax\n"
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"movl %%ecx, %%edx\n"
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"lock; cmpxchg8b %1"
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: "=&A"(original)
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: "m"(a->value)
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);
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return original;
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#endif
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}
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void zpl_atomic64_store(zpl_atomic64 *a, zpl_atomicarg(zpl_i64) value) {
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#if defined(ZPL_ARCH_64_BIT)
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a->value = value;
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#else
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zpl_atomicarg(zpl_i64) expected = a->value;
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__asm__(
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"1: cmpxchg8b %0\n"
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" jne 1b"
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: "=m"(a->value)
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: "b"((zpl_atomicarg(zpl_i32))value), "c"((zpl_atomicarg(zpl_i32))(value >> 32)), "A"(expected)
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);
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#endif
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}
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zpl_i64 zpl_atomic64_compare_exchange(zpl_atomic64 *a, zpl_atomicarg(zpl_i64) expected, zpl_atomicarg(zpl_i64) desired) {
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#if defined(ZPL_ARCH_64_BIT)
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zpl_atomicarg(zpl_i64) original;
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__asm__(
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"lock; cmpxchgq %2, %1"
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: "=a"(original), "+m"(a->value)
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: "q"(desired), "0"(expected)
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);
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return original;
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#else
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zpl_atomicarg(zpl_i64) original;
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__asm__(
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"lock; cmpxchg8b %1"
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: "=A"(original), "+m"(a->value)
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: "b"((zpl_atomicarg(zpl_i32))desired), "c"((zpl_atomicarg(zpl_i32))(desired >> 32)), "0"(expected)
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);
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return original;
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#endif
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}
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zpl_i64 zpl_atomic64_exchange(zpl_atomic64 *a, zpl_atomicarg(zpl_i64) desired) {
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#if defined(ZPL_ARCH_64_BIT)
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zpl_atomicarg(zpl_i64) original;
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__asm__(
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"xchgq %0, %1"
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: "=r"(original), "+m"(a->value)
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: "0"(desired)
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);
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return original;
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#else
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zpl_atomicarg(zpl_i64) original = a->value;
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for (;;) {
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zpl_atomicarg(zpl_i64) previous = zpl_atomic64_compare_exchange(a, original, desired);
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if (original == previous)
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return original;
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original = previous;
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}
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#endif
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}
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zpl_i64 zpl_atomic64_fetch_add(zpl_atomic64 *a, zpl_atomicarg(zpl_i64) operand) {
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#if defined(ZPL_ARCH_64_BIT)
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zpl_atomicarg(zpl_i64) original;
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__asm__(
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"lock; xaddq %0, %1"
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: "=r"(original), "+m"(a->value)
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: "0"(operand)
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);
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return original;
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#else
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for (;;) {
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zpl_atomicarg(zpl_i64) original = a->value;
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if (zpl_atomic64_compare_exchange(a, original, original + operand) == original)
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return original;
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}
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#endif
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}
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zpl_i64 zpl_atomic64_fetch_and(zpl_atomic64 *a, zpl_atomicarg(zpl_i64) operand) {
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#if defined(ZPL_ARCH_64_BIT)
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zpl_atomicarg(zpl_i64) original;
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zpl_atomicarg(zpl_i64) tmp;
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__asm__(
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"1: movq %1, %0\n"
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" movq %0, %2\n"
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" andq %3, %2\n"
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" lock; cmpxchgq %2, %1\n"
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" jne 1b"
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: "=&a"(original), "+m"(a->value), "=&r"(tmp)
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: "r"(operand)
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);
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return original;
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#else
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for (;;) {
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zpl_atomicarg(zpl_i64) original = a->value;
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if (zpl_atomic64_compare_exchange(a, original, original & operand) == original)
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return original;
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}
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#endif
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}
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zpl_i64 zpl_atomic64_fetch_or(zpl_atomic64 *a, zpl_atomicarg(zpl_i64) operand) {
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#if defined(ZPL_ARCH_64_BIT)
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zpl_atomicarg(zpl_i64) original;
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zpl_atomicarg(zpl_i64) temp;
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__asm__(
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"1: movq %1, %0\n"
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" movq %0, %2\n"
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" orq %3, %2\n"
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" lock; cmpxchgq %2, %1\n"
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" jne 1b"
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: "=&a"(original), "+m"(a->value), "=&r"(temp)
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: "r"(operand)
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);
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return original;
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#else
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||
|
|
for (;;) {
|
||
|
|
zpl_atomicarg(zpl_i64) original = a->value;
|
||
|
|
if (zpl_atomic64_compare_exchange(a, original, original | operand) == original)
|
||
|
|
return original;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
#else
|
||
|
|
#error TODO: Implement Atomics for this CPU
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
zpl_b32 zpl_atomic32_spin_lock(zpl_atomic32 *a, zpl_isize time_out) {
|
||
|
|
zpl_atomicarg(zpl_i32) old_value = zpl_atomic32_compare_exchange(a, 1, 0);
|
||
|
|
zpl_i32 counter = 0;
|
||
|
|
while (old_value != 0 && (time_out < 0 || counter++ < time_out)) {
|
||
|
|
zpl_yield_thread();
|
||
|
|
old_value = zpl_atomic32_compare_exchange(a, 1, 0);
|
||
|
|
zpl_mfence();
|
||
|
|
}
|
||
|
|
return old_value == 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void zpl_atomic32_spin_unlock(zpl_atomic32 *a) {
|
||
|
|
zpl_atomic32_store(a, 0);
|
||
|
|
zpl_mfence();
|
||
|
|
}
|
||
|
|
|
||
|
|
zpl_b32 zpl_atomic64_spin_lock(zpl_atomic64 *a, zpl_isize time_out) {
|
||
|
|
zpl_atomicarg(zpl_i64) old_value = zpl_atomic64_compare_exchange(a, 1, 0);
|
||
|
|
zpl_atomicarg(zpl_i64) counter = 0;
|
||
|
|
while (old_value != 0 && (time_out < 0 || counter++ < time_out)) {
|
||
|
|
zpl_yield_thread();
|
||
|
|
old_value = zpl_atomic64_compare_exchange(a, 1, 0);
|
||
|
|
zpl_mfence();
|
||
|
|
}
|
||
|
|
return old_value == 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void zpl_atomic64_spin_unlock(zpl_atomic64 *a) {
|
||
|
|
zpl_atomic64_store(a, 0);
|
||
|
|
zpl_mfence();
|
||
|
|
}
|
||
|
|
|
||
|
|
zpl_b32 zpl_atomic32_try_acquire_lock(zpl_atomic32 *a) {
|
||
|
|
zpl_atomicarg(zpl_i32) old_value;
|
||
|
|
zpl_yield_thread();
|
||
|
|
old_value = zpl_atomic32_compare_exchange(a, 1, 0);
|
||
|
|
zpl_mfence();
|
||
|
|
return old_value == 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
zpl_b32 zpl_atomic64_try_acquire_lock(zpl_atomic64 *a) {
|
||
|
|
zpl_atomicarg(zpl_i64) old_value;
|
||
|
|
zpl_yield_thread();
|
||
|
|
old_value = zpl_atomic64_compare_exchange(a, 1, 0);
|
||
|
|
zpl_mfence();
|
||
|
|
return old_value == 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(ZPL_ARCH_32_BIT)
|
||
|
|
|
||
|
|
void* zpl_atomic_ptr_load(zpl_atomic_ptr const *a) {
|
||
|
|
return (void *)cast(zpl_intptr)zpl_atomic32_load(cast(zpl_atomic32 const *)a);
|
||
|
|
}
|
||
|
|
void zpl_atomic_ptr_store(zpl_atomic_ptr *a, zpl_atomicarg(void *)value) {
|
||
|
|
zpl_atomic32_store(cast(zpl_atomic32 *)a, cast(zpl_atomicarg(zpl_i32))cast(zpl_intptr)value);
|
||
|
|
}
|
||
|
|
void* zpl_atomic_ptr_compare_exchange(zpl_atomic_ptr *a, zpl_atomicarg(void *)expected, zpl_atomicarg(void *)desired) {
|
||
|
|
return (void *)cast(zpl_intptr)zpl_atomic32_compare_exchange(cast(zpl_atomic32 *)a, cast(zpl_atomicarg(zpl_i32))cast(zpl_intptr)expected, cast(zpl_atomicarg(zpl_i32))cast(zpl_intptr)desired);
|
||
|
|
}
|
||
|
|
void* zpl_atomic_ptr_exchange(zpl_atomic_ptr *a, zpl_atomicarg(void *)desired) {
|
||
|
|
return (void *)cast(zpl_intptr)zpl_atomic32_exchange(cast(zpl_atomic32 *)a, cast(zpl_atomicarg(zpl_i32))cast(zpl_intptr)desired);
|
||
|
|
}
|
||
|
|
void* zpl_atomic_ptr_fetch_add(zpl_atomic_ptr *a, zpl_atomicarg(void *)operand) {
|
||
|
|
return (void *)cast(zpl_intptr)zpl_atomic32_fetch_add(cast(zpl_atomic32 *)a, cast(zpl_atomicarg(zpl_i32))cast(zpl_intptr)operand);
|
||
|
|
}
|
||
|
|
void* zpl_atomic_ptr_fetch_and(zpl_atomic_ptr *a, zpl_atomicarg(void *)operand) {
|
||
|
|
return (void *)cast(zpl_intptr)zpl_atomic32_fetch_and(cast(zpl_atomic32 *)a, cast(zpl_atomicarg(zpl_i32))cast(zpl_intptr)operand);
|
||
|
|
}
|
||
|
|
void* zpl_atomic_ptr_fetch_or(zpl_atomic_ptr *a, zpl_atomicarg(void *)operand) {
|
||
|
|
return (void *)cast(zpl_intptr)zpl_atomic32_fetch_or(cast(zpl_atomic32 *)a, cast(zpl_atomicarg(zpl_i32))cast(zpl_intptr)operand);
|
||
|
|
}
|
||
|
|
zpl_b32 zpl_atomic_ptr_spin_lock(zpl_atomic_ptr *a, zpl_isize time_out) {
|
||
|
|
return zpl_atomic32_spin_lock(cast(zpl_atomic32 *)a, time_out);
|
||
|
|
}
|
||
|
|
void zpl_atomic_ptr_spin_unlock(zpl_atomic_ptr *a) {
|
||
|
|
zpl_atomic32_spin_unlock(cast(zpl_atomic32 *)a);
|
||
|
|
}
|
||
|
|
zpl_b32 zpl_atomic_ptr_try_acquire_lock(zpl_atomic_ptr *a) {
|
||
|
|
return zpl_atomic32_try_acquire_lock(cast(zpl_atomic32 *)a);
|
||
|
|
}
|
||
|
|
|
||
|
|
#elif defined(ZPL_ARCH_64_BIT)
|
||
|
|
|
||
|
|
void* zpl_atomic_ptr_load(zpl_atomic_ptr const *a) {
|
||
|
|
return (void *)cast(zpl_intptr)zpl_atomic64_load(cast(zpl_atomic64 const *)a);
|
||
|
|
}
|
||
|
|
void zpl_atomic_ptr_store(zpl_atomic_ptr *a, zpl_atomicarg(void *)value) {
|
||
|
|
zpl_atomic64_store(cast(zpl_atomic64 *)a, cast(zpl_i64)cast(zpl_intptr)value);
|
||
|
|
}
|
||
|
|
void* zpl_atomic_ptr_compare_exchange(zpl_atomic_ptr *a, zpl_atomicarg(void *)expected, zpl_atomicarg(void *)desired) {
|
||
|
|
return (void *)cast(zpl_intptr)zpl_atomic64_compare_exchange(cast(zpl_atomic64 *)a, cast(zpl_i64)cast(zpl_intptr)expected, cast(zpl_i64)cast(zpl_intptr)desired);
|
||
|
|
}
|
||
|
|
void* zpl_atomic_ptr_exchange(zpl_atomic_ptr *a, zpl_atomicarg(void *)desired) {
|
||
|
|
return (void *)cast(zpl_intptr)zpl_atomic64_exchange(cast(zpl_atomic64 *)a, cast(zpl_i64)cast(zpl_intptr)desired);
|
||
|
|
}
|
||
|
|
void* zpl_atomic_ptr_fetch_add(zpl_atomic_ptr *a, zpl_atomicarg(void *)operand) {
|
||
|
|
return (void *)cast(zpl_intptr)zpl_atomic64_fetch_add(cast(zpl_atomic64 *)a, cast(zpl_i64)cast(zpl_intptr)operand);
|
||
|
|
}
|
||
|
|
void* zpl_atomic_ptr_fetch_and(zpl_atomic_ptr *a, zpl_atomicarg(void *)operand) {
|
||
|
|
return (void *)cast(zpl_intptr)zpl_atomic64_fetch_and(cast(zpl_atomic64 *)a, cast(zpl_i64)cast(zpl_intptr)operand);
|
||
|
|
}
|
||
|
|
void* zpl_atomic_ptr_fetch_or(zpl_atomic_ptr *a, zpl_atomicarg(void *)operand) {
|
||
|
|
return (void *)cast(zpl_intptr)zpl_atomic64_fetch_or(cast(zpl_atomic64 *)a, cast(zpl_i64)cast(zpl_intptr)operand);
|
||
|
|
}
|
||
|
|
zpl_b32 zpl_atomic_ptr_spin_lock(zpl_atomic_ptr *a, zpl_isize time_out) {
|
||
|
|
return zpl_atomic64_spin_lock(cast(zpl_atomic64 *)a, time_out);
|
||
|
|
}
|
||
|
|
void zpl_atomic_ptr_spin_unlock(zpl_atomic_ptr *a) {
|
||
|
|
zpl_atomic64_spin_unlock(cast(zpl_atomic64 *)a);
|
||
|
|
}
|
||
|
|
zpl_b32 zpl_atomic_ptr_try_acquire_lock(zpl_atomic_ptr *a) {
|
||
|
|
return zpl_atomic64_try_acquire_lock(cast(zpl_atomic64 *)a);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
ZPL_END_C_DECLS
|